High-speed serial interface protocols for microwave data converters

ESIstream protocols are proposed and maintained by Teledyne-e2v Semiconductors, but they are not proprietary and everyone is free to adopt them to take advantage of their efficiency and ease of use.

High-speed serial interface protocols for microwave data converters

The ESIstream protocol is born from a strong need of the following combination:

  • Reduce data overhead on serial links.

  • Increase rate of useful data when linking high-speed data converters operating at GSps sampling rate with a FPGA.

  • Simplify hardware implementation to be built on RF SiGe technologies

ESIstream 14B/16B main benefits

  • 87.5% EFFICIENCY
  • Deterministic and low link latency
  • Minimal hardware implementation
  • Multi-devices synchronization
  • Demonstrated lane rate up to 12.8 Gbps
  • Multi-lanes synchronization
  • Guaranteed DC balance, ±16 bits running disparity
  • Maximum run length of 32 bits
  • Synchronization monitoring
ESIstream 14B/16B package
ESIstream 14B/16B main benefits

ESIstream 14B/16B protocol specification

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ESIstream 62B/64B main benefits

  • 96.875% EFFICIENCY
  • Deterministic and low link latency
  • Minimal hardware implementation
  • Multi-devices synchronization
  • Demonstrated lane rate up to 12.8 Gbps
  • Multi-lanes synchronization
  • Guaranteed DC balance, ±64 bits running disparity
  • Maximum run length of 64 bits
  • Synchronization monitoring
ESIstream 62B/64B Package
ESIstream 62B/64B main benefits

ESIstream 62B/64B protocol specification

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