Check this video to learn how to simulate the EV12AQ600 ADC ESIstream serial interface using Vivado simulator and testbench available in each ESIstream package (KU FPGA, Versal ACAP…).​

An ESIstream package can contain several TCL scripts. The number 16, 32 or 64 indicates the serialization or deserialization width used to configure the User data width parameter value of the Xilinx Gigabit transceiver IP, shown on the picture below.

The selection of user data width (16, 32 or 64) is a trade-off between minimum link latency, minimum logic resources, and frames rate in the FPGA.​​

Check your schematic or PCB layout. It is possible that the polarity of the HSSLs differential pairs have been swapped (inverted) to simplify the layout. In this case, the COMMA of the ESIstream Synchronization Sequence is inverted and it generates a shift of 2 ESIstream frames compared to other HSSLs at ESIstream receiver (RX) outputs.

It should be possible to compensate for this polarity swap in the FPGA, or in the ADC / DAC Gigabit Transceiver.​

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It depends on the implementation:

  • ESIstream RX IP running at a lane rate less than 6.25 Gbps can use a 16-bit user data path implementation in FPGA logic
    • Using 16-bit implementation: 225 LUTs per lane & 231 FFs per lane with an output buffer using BRAMs.
  • ESIstream RX IP running at lane rate greater than 6.25 Gbps requires a 32-bit or a 64-bit user data path implementation in FPGA logic.
    • Using 32-bit implementation:
      • 444 LUTs per lane & 314 FFs per lane with an output buffer using BRAMs.
      • ​ 495 LUTs per lane & 371 FFs per lane with an output buffer using shift registers instead of BRAMs.
    • Using 64-bit implementation:
      • 661 LUTs per lane & 527 FFs per lane with an output buffer using BRAMs.

Further optimization is possible using higher speed grade FPGA allowing removing some pipelining in the logic and so FFs utilization.

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Project Device Package Speed grade Number of Lanes Max lane rate [Gbps] LUTs KU060 (331680) FFs KU060 (663360) KU060 LUTs % KU060 FFs %
16b xcku060 FFVA1517 -1 8 6.25 1803 1854 0.54 0.28
32b xcku060 FFVA1517 -1 8 12.5 3551 2514 1.07 0.38
32b_dl xcku060 FFVA1517 -1 8 12.5 3543 2510 1.07 0.38
64b_dl xcku060 FFVA1517 -1 8 12.5 5291 4222 1.60 0.64​

JESD204 IP CORE V7.2

Device GT Number of Lanes LUTs FFs 18k BRAMs FIFO implementation
xcku040-ffva1156-2-e RX GTH3E 8 7399 6501 0 −

ESIstream V2-2 32-bit

Device GT Number of Lanes LUTs FFs 18k BRAMs FIFO implementation
xcku040-ffva1156-2-e RX GTH3E 8 3533 2510 8 Dual clock built-in
xcku040-ffva1156-2-e RX GTH3E 8 3963
-46% 		2974
-54% 		0 Single-clock shift-register

The ESIstream protocol itself is not constrained, it runs well at lower data rates such as 3.125 Gbps and as low as 500 Mbps (e.g. shown on Microsemi RTG4 FPGA). Much higher data rates are supported by the latest industrial FPGAs from Xilinx and Intel as speed is determined by hardware & especially transceiver performances. ​ESIstream is successfully implemented up to 12.8 Gbps on major platforms.

ESIstream has been developed with efficiency and simplicity in mind especially supporting Teledyne-​​e2v's traditional hi-rel markets. For reliable implementation, the right transceiver and good hardware design must be applied. As it is an open-source protocol, ESIstream allows users to modify and ruggedized protocol logic for harsh and high reliability environments.