ESIstream protocol is born from a severe need of the following combination:

• Increase rate of useful data, when linking data converters operating at GSps speeds with FPGAs on a serial interface, reducing data overhead on serial links, as low as possible.
• Simplified hardware implementation, simple enough to be built on RF SiGe technologies.

ESIstream provides an efficient High-Speed serial interface based on a 14B/16B encoding using a Linear Feedback Shift Register (LFSR) scrambling unit, a Disparity Bit (DB) to ensure deterministic DC balance transmission and a toggling bit, the Clk Bit (CB), to enable synchronization monitoring.

It is license-free and supports in particular serial communication between FPGAs and High-Speed data converters.

However, ESIstream can be used in any system requiring a serial interface. For instance, between two FPGAs or two ASICs.

An ESIstream system is made up of the following elements.

• A transmitter (TX) can be an ADC or any Logic Devices (LD) such as a FPGA or an ASIC.
• A receiver (RX) can be a DAC or any Logic Devices such as a FPGA or an ASIC.
• A number of serial lanes (L ≥ 1) to transmit serial data.
• A synchronization signal (sync) used to initialize the communication and synchronize the transmitter and receiver. On a single device, only one occurrence of the SYNC signal is necessary between the transmitter and the receiver even if multiple serial links are implemented.

There is no clock lane in a serial interface. For each lane, the receiver should recover the clock from the data. ​